The present invention relates to a memory cell for use in a random access memory (RAM), and more particularly, to such a cell that is radiation hard.
A typical RAM cell comprises two inverters, with each inverter comprising a pair of metal oxide semiconductor (MOS) transistors. Each pair has a P-conductivity type channel (PMOS) transistor and a N-conductivity type channel (NMOS) transistor. The RAM may be used while exposed to radiation, such as cosmic rays, that produces electrons and holes. This charge can change the charge stored on the gate capacitance of a MOS transistor which can cause a "single event upset" (SEU), which is a change in state of the memory cell.
It is known from U.S. patent application Ser. No. 665,008, filed Oct. 26, 1984, to use the resistance of buried contact diodes coupled in series with the drains of the PMOS transistors and the resistance of gate-drain tied intrinisic mode MOS transistors coupled in series with the drains of the NMOS transistors to raise the critical charge (Q.sub.c) necessary to cause an SEU. This is achieved since the time constant of the cell is increased by said resistances. Since the radiation-induced current only exists briefly, it cannot cause a change in state of a cell with a time constant that is large relative to the duration of the radiation. However, an extra masking step is required during ion implantation of the intrinsic mode transistors to adjust their threshold voltage to be nearly zero. Further, the circuit of said patent is constructed on sapphire, which is expensive compared with bulk silicon.